The desirability of testing and burning-in integrated circuits at the wafer level is of particular interest since determination of failures at this early stage can significantly reduce costs. Wafer burn-in is an attractive technique for providing known good die for packaging in semiconductor modules including a large number of chips.
Commonly assigned U.S. Pat. No. 5,600,257, to J. Leas, et al. (the "'257 patent"), discloses an arrangement for simultaneously testing or simultaneously burning-in all the product chips on an integrated circuit wafer. The arrangement provides thermal matching between a test head and the semiconductor wafer, large scale power distribution, and electronic means to remove shorted product chips from the power distribution structure. In one embodiment the test head comprises a glass ceramic substrate, a material closely thermally matched to silicon, with test chips on one side and probes on the other side. The glass ceramic substrate has a sufficient number of thick copper power planes to provide current to each product chip on an integrated circuit wafer with a minimal voltage drop. The test chips have voltage regulators to provide a tightly controlled Vdd and ground voltage to each chip on the product wafer that is substantially independent of the current drawn by that chip and its neighbors, and substantially independent of the presence of shorted chips on the product wafer. The regulators can also be used to disconnect power to shorted chips.
Commonly assigned U.S. patent application Ser. No. 08/882,989, now U.S. Pat. No. 6,020,750, provides an improved arrangement in which a plurality of glass ceramic substrates are tiled together to provide a large area test head.
However, both of these arrangements provide tester chips in such close proximity to the product wafer that the tester chips operate at about the same temperature as the wafer during burn-in, limiting the lifetime of the tester chips. In addition, both of these arrangements for contacting all the chips on a wafer involve expensive hardware, and neither permits contact to a range of chip types that have different contact footprints.
For example, when improved technology permits a chip design to go through a "shrink," decreasing its size and increasing the number of chips that can be fabricated on a wafer, it should not be necessary to redesign an entire test head to accommodate the increased number of chips and the new chip footprint. Thus a better solution is needed that both provides for improved tester chip lifetime and greater flexibility and lower cost for personalizing contacts, and this solution is provided by the following invention.